Andrew
arx@tech.lgbt
<p>Manchester, music, retro technology (especially BBC Micro), comedy, sci-fi, animation, snooker/pool, fluffy animals, trying to be a vegetarian but not in a preachy way. private static void.</p>
Posts
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New cat discovered, they’re moody af, awesome.
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Gotta love these employee surveys. “I feel well-informed about x…” How can I possibly know that? I don’t know what I don’t know, and there’s always something I don’t know.
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Welp, I&#39;m not quite sure how but I managed to simplify my cruddy bus logic. And now I know my formative video display chip is reading data correctly from memory coz I&#39;ve made it emit it straight back out on its data out lines. I&#39;m still not at all confident with the Verilog and the behaviour of stuff... might need an expert in Verilog FPGA stuff to take a looksee and advise, so that I don&#39;t blunder into a distressing mess. *flutter* #Retrocomputing
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The palette register will be 32-entries, in part coz one of the modes will pair each of the 8 bits from the bitmap bytes with the lower/upper nybble of accompanying attribute bytes. Not unlike VGA text mode, except there’s only bandwidth for 40 columns. But that’s still like the VIC-II on crack. Each palette entry is 6-bit (c0-5) plus an ‘expand’ bit that says how to convert c0-5 into 12-bit RGB. If expand = 0 then Red = (c1,c0,c1,c0), Green = (c3,c2,c3,c2), Blue = (c5,c4,c5,c4) which is basica...
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I realise this is prolly a state machine, so I gotta be totally clear what these states are and what has to happen when they occur.
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Slut Gimmick Zone, Act 2.
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By &#39;eck, I think this thing might actually be loading and caching the character codes on even raster lines, and then on odd raster lines using those to fetch character definitions. I think I might actually be able to pull this off.
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Pardon my swear but holy tittyfucking shit!!! #retrocomputing
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Thinking which heavily idealised day from my childhood I’d most like as my loop in Heaven. But then, what about all the other people made to participate? What kind of day is it that’s the best for us all?
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Trying to get this VDG logic as minimal and as fluent in my head as possible before I sit back down at the computer to try to get it properly nailed, excluding sprites. One of its party tricks is to make 4 medium-width pixels per word (b7 to b0) from palette indexes (b7, b3-0); (b6, b3-0); (b5, b3-0); (b4-0). This means each contiguous group of 4 horizontal pixels, whilst 1bpp, choses 1 of 16 possible pairs of colours as its basis. With careful graphic design and choice of palette, one can ape...
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Realise I can use the Basys-3’s 16 switches as non-volatile boot settings.
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The newly discovered Clayhill Vineyard in Althorne.
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Lookit the dog menu. &lt;3
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I wonder what this is. Track inspection gizmotronics?
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Thinking I adapt the Beeb’s hardware design a tad, ditching the shadow RAM concept in favour of making the video memory just a special case of sideways RAM. Reducing the screen to 200 logical lines will make it fit within 16kB. Line doubling will make it 400, within a 640x480 at 25MHz VGA. Line doubling how exactly? Well… I could alternate between character codes and character definitions on even and odd lines, using an 80 byte buffer. No need for badlines that freeze the CPU, provided I run th...
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How quickly could a proof of P=NP be verified? Would it necessarily reference itself?
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Symmetry happens when you have more dimensions to fill than you have information to go around, so you have to reuse at least one bit of it. The first step of intelligence is to figure out what it is that’s being reused.
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Right, let&#39;s do this properly. Apparently these programmable logic devices prefer clock enable signals that are high only for the duration of a master clock cycle, because power, synchronisation, ease of synthesis etc. That&#39;s why I kept seeing that design pattern in all the other retro computer Verilog projects I&#39;ve been studying. So here we are with the beginnings of my own custom video display generator, creating all the clock signals for driving the CPU and system bus,...
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Summat like this would be handy, if I could do it.
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A sound chip that reads tracker-like data from memory all by itself, in between the CPU cycles.
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Masters of the Uwuniverse.
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Viewer discretion advised: Today’s crappy world reflects the attitudes and standards of its time.
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Away from the PC, I’m having a bash at designing an ASCII font whose printable characters all leave the most and least significant bits clear, so that they can be used as colour attributes when required. Imagine the BBC Micro’s mode 0 but with four colours selectable per line per character. Handy for 80-column program listing with highlighted keywords and errors. Characters 0-31 will hold the values 0-255, because the bitmapped graphics mode will be a special case of character mode comprising 2...