Welp, I'm not quite sure how but I managed to simplify my cruddy bus logic. And now I know my formative video display chip is reading data correctly from memory coz I've made it emit it straight back out on its data out lines. I'm still not at all confident with the Verilog and the behaviour of stuff... might need an expert in Verilog FPGA stuff to take a looksee and advise, so that I don't blunder into a distressing mess. *flutter* #Retrocomputing