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  New LUTI2/LUTI4 SIMD instructions on the Apple M6 are fast! 4 per cycle throughput, 2 cycle latency (on the S-cores), matching TBL (on all cores). Nice for pivco-huffman (and presumably some other SIMD compression schemes). There also seems to be some SIMD/FP FMIN/FMAX fusion (for clamps and reductions), but tragically not for SIMD integer min/max. Other neat new fusions: SIMD CMGT/CMEQ + AND/ORR and scalar shift (unsigned or by imm) + AND #imm. https://docsmirror.github.io/A64/2025-06/luti2_a...

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  "Apple M3 GPU reverse engineering progress", by Anna Maniscalco, Alyssa Milburn and Evan Tang https://youtu.be/TPwe53kCJuM?t=2133 (If you're curious, the WIP ISA reversing and disassembler lives at https://github.com/TellowKrinkle/applegpu/tree/M3 )

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  What instructions would you like to see added to x86 or ARM? Personally, I want an ADD3 or an add-and-accumulate SIMD operation. A lot of algorithms are dominated by additions, and getting two adds with one instruction could help a lot. The closest instruction is SABA (signed-absolute-difference-and-accumulate), so I'm assuming this would be practical. I also have AVX-512 embedded rounding (and exception) control envy, but idk if ARM can find the bits for that with fixed-size instructions.

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  Marcin Żukowski’s PivCo-Huffman paper inspired me to revisit an Oodle-like 12-stream Huffman decoder for Apple CPUs that I experimented with in 2022. The same old kernel manages a pretty flat 5GB/s to 5.1GB/s on Apple M4, which did beat PivCo-Huffman, on one or two files, at the time of the paper. But with @rygorous@mastodon.gamedev.place's and Marcin's improvements, the updated PivCo-Huffman code reliably wins. And it doesn't need 31 GPRs. Very exciting work. https://gist.github.c...

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  Andreas Abel added latency, throughput, and port usage data for Emerald Rapids, Meteor Lake, Arrow Lake, and Zen 5 to https://uops.info/table.html 🎉