Post by @NotEasyBeingGreen@slrpnk.net

2026-10-18 07:07 UTC

The 8088 CPU (the one from the original IBM PC) had special string scanning support with both instructions and registers. The SI (source index) and DI (destination index) were such registers, and a bunch of instructions related. However, specialized instructions take die area on the CPU. In the 1980s a movement based on the observation that most sophisticated instructions were not used much, and it would be better to concentrate on making very common operations (like add, load, store, shift, or whatever) fast. That started reduced-instruction set computing (RISC). RISC was so successful that x86 chips switched to the model with a RISC-like core and implementing more sophisticated fuctions in “microcode”. Today Linux can load microcode, which is basically patching the firmware of the CPU itself. Anyway, of course the drive towards RISC ended as people realized that some advanced functionality is really useful. In the 1990s and 2000s this was focused around new limitations: it was impossible to get higher frequencies so running a single core couldn’t get faster. CPUs added SIMD (single instruction, multiple data) support as well as hyperthreading. Now… revisiting string operations and adding CPU support would be possible. Engineers at CPU design shops look at how their chip space is used and optimize the die area for instruction sets and also registers, cache, and so on. But my guess is that it doesn’t make sense or it would have happened a decade ago already.

Replies (1)

@MangoCats@feddit.it 2026-10-18 13:29

RISC was so successful I would say popular rather than successful, but yeah, I was “actively” in the assembly code around then. Around 2010 I was working with NIOS cores on FPGAs, which were ultra-flexible (sort of the ultimate microcode embodiment), but not really efficient or performant the way a fixed ARM core is. At the time Xilinx was promising ARM cores on-chip beside the FPGAs “real soon” - it took a while, but they finally delivered and that is a nice arrangement when you need specialized processing, which most projects I have seen implemented with those ARM+FPGA uZed and similar boards don’t really need and they can better be implemented on a simple ARM core system, maybe with a few built-in timer-latches, instead. In the 2007 timeframe we were looking to squeeze performance out of an algorithm to bring an analysis time down from hours to 5 minutes or less, massive parallelism was on the table but expensive - not unaffordable in the application - but unwieldy in the space / bandwidth taken by the hardware. SIMD, MIMD - the compiler optimizers seemed to be doing well enough with those to get what was possible, but we were still over 2 hours. Finally, a code review of the profiler identified bottleneck turned up a queer looking nested loop structure that was causing cache misses on the inner loop. We restructured that and sped things up 100x, 5 minute execution on a laptop, more like 2 minutes on the quad-core workstation target. I think the “chief scientist” was disappointed that we wouldn’t be building an array of 100 workstations to crunch the numbers in parallel. RAM is fast, cache is faster.

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