Running out of DSP slices on your FPGA? I’ve been experimenting with Low-Rank Approximations for 3x3 Convolutions to solve exactly that. My latest project replaces standard matrix multiplications with learned, hardware-friendly bit-shifts. The result: • 33% reduction in DSP usage (2 Muls instead of 3) • <1% error (SSIM > 0.99) • Ideal for SWaP-C constrained edge perception. https://www.dockerr.blog/blog/lowrank-hardware-approximation #FPGA #VHDL #EmbeddedSystems #ComputerVision #EdgeAI #OpenScience #Engineering